PRESS RELEASE

For more information contact:

Coby Zelnik Sagantec North America Tel: 1.510.360.5200 x110 Email: coby@sagantec.com http://www.sagantec.com

Wendy Truax Lee Public Relations Tel: 1.503.672.9073 Email: wendy@leepr.com

FREMONT, Calif. -- June 14, 2001 -- Sagantec North America announced today that attendees of the Design Automation Conference (DAC) can receive a complimentary copy of the new book Hard IP: An Introduction to ROI for VLSI Chip Designs by Peter Rohr, Ph.D. The book will be available at Sagantec's booth, #3021, upon request, until supply runs out. DAC takes place from June 18 to June 21 at the Las Vegas Convention Center. It is the first book to address the challenges of hard IP re-use in VLSI chip design.

Rohr's book focuses on both hard IP retargeting and physical layout optimization for very deep submicron (VDSM) technologies (0.25 micron and below). Rohr looks at the pros and cons of porting proven IC designs to more advanced processes through both soft IP or hard IP reuse based on polygon compaction. Hard IP retargeting starts with an existing design and ports it to a more advanced process by using software to enforce the layout design rules of the new fabrication technology while at the same time improving performance such as speed, power dissipation, reliability, fabrication yield and signal integrity.

Performance optimization through layout manipulation for VDSM technologies are also discussed. Rohr demonstrates that issues such as signal integrity, electromigration, interconnect-to-interconnect capacitive loading and excessive power dissipation are becoming so important that layout optimization is now necessary, and no longer a luxury.

Hein van der Wildt, president and CEO of Sagantec, said, "To date, literature addressing design productivity of complex, high performance VLSI chips has focused solely on working at higher levels of abstraction through synthesis. What is lacking is a discussion addressing the physical layout challenges that grow worse with every advance into deeper sub-micron technology. This is the first book that addresses hard IP retargeting, an alternative which will allow designers to develop these chips both rapidly and predictably."

The book will retail for $50.00 and will be widely available in July at technical bookstores and on on-line retailers.

About the Author
Peter Rohr, Ph.D has over 30 years of experience in electronic design automation and in fields such as high-speed digital and GPS circuit design, applications of DSP, microprocessors, analog circuits, silicon compilation and VLSI chip DFT. As a member of the Graduate Faculty of the Department of Electrical Engineering at Louisiana State University, he has lectured on analog circuit design and semiconductor physics. As a consultant he has conducted workshops on VLSI DFT and deep sub-micron methodologies. Recently he was vice president of business development at Sagantec. Rohr is now president of MATTERHORN CONSULTING specializing in international business development.

About Sagantec
Sagantec provides software, methodologies and services that enable rapid implementation reuse and design closure for full custom physical designs in sub-wavelength technologies. The company is working closely with its semiconductor partners and customers to ensure that its products work with the most aggressive technologies of 0.13 micron and below. Sagantec products are specifically designed to accelerate the physical design process of high performance/low power CPUs, and DSPs, dedicated and embedded memories, and analog/mixed-signal circuits. Privately held and funded, Sagantec was founded in 1993 in Israel. Its Corporate headquarters for sales, marketing, technical services and applications organization is located at 46485 Landing Parkway, Fremont, Calif. 94538. Telephone: (510) 360-5200. Facsimile: (510) 360-5255. On the web at: http://www.sagantec.com.